The present invention generally relates to phase locked loop (PLL) synthesizer circuits, and more particularly to a PLL synthesizer circuit in which an output signal frequency of a voltage controlled oscillator can be switched at a high speed.
FIG. 1 shows an example of a conventional PLL synthesizer circuit. The PLL synthesizer circuit includes a crystal oscillator 1, a reference frequency divider 2, a comparison frequency divider 3, a phase comparator 4, a charge pump circuit 5, a lowpass filter 6, and a voltage controlled oscillator (VCO) 7 which are connected as shown. The reference frequency divider 2 frequency-divides an output signal of the crystal oscillator 1 and outputs a reference signal Sr. The comparison frequency divider 3 frequency-divides an output signal SVCO of the VCO 7 and outputs a comparison signal Sp. The phase comparator 4 compares the phases of the reference signal Sr and the comparison signal Sp, and outputs signals for adjusting an output voltage VLPF of the lowpass filter 6 via the charge pump circuit 5 so that the phase error becomes zero. The charge pump circuit 5 outputs a signal SCP. The output signal SVCO of the VCO 7 is locked to a target frequency, and this output signal SVCO of the VCO 7 is output as an output signal of the PLL synthesizer circuit.
The phase comparator 4 is of the so-called phase discrimination type, and discriminates the phase lag and phase lead of the comparison signal Sp with respect to the reference signal Sr. The phase comparator 4 outputs a signal .phi.r which indicates the phase lag of the comparison signal Sp with respect to the reference signal Sr and a signal .phi.p which indicates the phase lead of the comparison signal Sp with respect to the reference signal Sr and a signal .phi.p. The signals .phi.r and .phi.p are output independently from the phase comparator 4.
For example, the charge pump circuit 5 and the lowpass filter 6 have a construction shown in FIG. 2. When the signals .phi.r and .phi.p both have a low level in FIG. 2, a PNP transistor 51 turns ON and an NPN transistor 52 turns OFF, thereby making a charging operation with respect to capacitors 61 and 62. On the other hand, when the signals .phi.r and .phi.p both have a high level in FIG. 2, the PNP transistor 51 turns OFF and the NPN transistor 52 turns ON, thereby making a discharging operation with respect to the capacitors 61 and 62. When the signal .phi.r has the high level and the signal .phi.p has the low level, the transistors 51 and 52 both turn OFF and the capacitors 61 and 62 enter a floating state. In this case, the charged voltages are held by the capacitors 61 and 62, and the output voltage VLPF of the lowpass filter 6 stabilizes.
FIGS. 3 and 4 are timing charts for explaining the operation of the charge pump circuit 5 of the conventional PLL synthesizer circuit shown in FIG. 1. FIG. 3 shows the timing chart for explaining the operation of the charge pump circuit 5 when the frequency dividing ratio of the comparison frequency divider 3 is increased from the state where the output signal SVCO of the VCO 7 is locked to a frequency f1 and the output signal SVCO locks to a frequency f2 which is greater than the frequency f1, where fr denotes the frequency of the reference signal Sr and Fp denotes the frequency of the comparison signal Sp. FIG. 4 shows the timing chart for explaining the operation of the charge pump circuit 5 when the frequency dividing ratio of the comparison frequency divider 3 is decreased from the state where the output signal SVCO of the VCO 7 is locked to the frequency f2 and the output signal SVCO locks to the frequency f1.
As may be seen from FIGS. 3 and 4, the falling edge of the phase comparison signal .phi.r is synchronized to the rising edge of the reference signal Sr regardless of whether the PLL synthesizer circuit is in the locked state or the unlocked state. In addition, the rising edge of the phase comparison signal .phi.p is synchronized to the rising edge of the comparison signal Sp regardless of whether the PLL synthesizer circuit is in the locked state or the unlocked state.
However, when the frequency dividing ratio of the comparison frequency divider 3 is increased from the state where the output signal SVCO of the VCO 7 is locked to the frequency f1 and state changes to the unlocked state where fr&gt;fp, the low-level period of the phase comparison signal .phi.r is enlarged by a width which is slightly greater than the phase delay of the comparison signal Sp with respect to the reference signal Sr as shown in FIG. 3 in a state where the falling edge of the phase comparison signal .phi.r remains synchronized to the rising edge of the reference signal Sr. In this case, the rising edge of the phase comparison signal .phi.p remains synchronized to the rising edge of the comparison signal Sp, and no change occurs as for the high-level period of the phase comparison signal .phi.p.
As a result, the charge pump circuit 5 intermittently turns ON the PNP transistor 51 in synchronism with the rising edge of the reference signal .phi.r, and intermittently supplies a charge voltage to the lowpass filter 6. Hence, the output voltage VLPF of the lowpass filter 6 rises, and the frequency of the output signal SVCO of the VCO 7 increases to the frequency f2.
When the frequency of the output signal SVCO of the VCO 7 rises to the frequency f2, the frequency fr of the reference signal Sr and the frequency fp of the comparison signal Sp become equal (that is, fr=fp), and the phase comparison signal .phi.r returns to a state which indicates that there is no phase error between the reference signal Sr and the comparison signal Sp. Consequently, the capacitances 61 and 62 of the lowpass filter 6 assume the floating state, and the charged voltage in the capacitors 61 and 62 are held. The output voltage VLPF of the lowpass filter 6 stabilizes to the voltage at which the frequency of the output signal SVCO of the VCO 7 becomes the frequency f2, and the frequency of the output signal SVCO of the VCO 7 is locked to the frequency f2.
On the other hand, when the frequency dividing ratio of the comparison frequency divider 3 is decreased from the state where the output signal SVCO of the VCO 7 is locked to the frequency f2 and state changes to the unlocked state where fr&lt;fp, the high-level period of the phase comparison signal .phi.p is enlarged by a width which is slightly greater than the phase lead of the comparison signal Sp with respect to the reference signal Sr as shown in FIG. 4 in a state where the falling edge of the phase comparison signal .phi.p remains synchronized to the rising edge of the reference signal Sr. In this case, the falling edge of the phase comparison signal .phi.r remains synchronized to the rising edge of the comparison signal Sp, and no change occurs as for the low-level period of the phase comparison signal .phi.r.
As a result, the charge pump circuit 5 intermittently turns ON the NPN transistor 52 in synchronism with the rising edge of the comparison signal Sp, and intermittently discharges the capacitors 61 and 62 of the lowpass filter 6. Hence, the output voltage VLPF of the lowpass filter 6 falls, and the frequency of the output signal SVCO of the VCO 7 decreases to the frequency f1.
When the frequency of the output signal SVCO of the VCO 7 falls to the frequency f1, the frequency fr of the reference signal Sr and the frequency fp of the comparison signal Sp become equal (that is, fr=fp), and the phase comparison signal .phi.p returns to a state which indicates that there is no phase error between the reference signal Sr and the comparison signal Sp. Consequently, the capacitances 61 and 62 of the lowpass filter 6 assume the floating state, and the charged voltage in the capacitors 61 and 62 are held. The output voltage VLPF of the lowpass filter 6 stabilizes to the voltage at which the frequency of the output signal SVCO of the VCO 7 becomes the frequency f1, and the frequency of the output signal SVCO of the VCO 7 is locked to the frequency f1.
When charging the capacitors 61 and 62 which form the lowpass filter 6 of the conventional PLL synthesizer circuit, the charging operation is intermittently carried out in synchronism with the reference signal Sr. In addition, the discharging operation is carried out intermittently in synchronism with the comparison signal Sp. For this reason, there is a problem in that the frequency of the output signal SVCO of the VCO 7 cannot be switched at a high frequency.
Presently, communication systems such as mobile telephone sets are all analog systems. However, when such communication systems are changed to digital systems, it becomes desirable to tune to a desired frequency at a high speed particularly in the case of a digital mobile telephone set. In other words, there is a demand to realize a PLL synthesizer circuit in which the lock-up time is extremely short.